The present invention relates to a manufacturing technology of a semiconductor device, and in particular, to an effective technology applied to manufacture of a semiconductor device having a package structure in which a semiconductor chip is sealed by a resin sealing body, and in which an external terminal electrically coupled to an electrode pad formed on a front surface of the semiconductor chip is exposed from a lower surface of the resin sealing body.
For example, Japanese Patent Laid-Open No. 2002-76040 (Patent Document 1) discloses a semiconductor device which has: a semiconductor chip; a plurality of electrode members; a plurality of coupling means which electrically couples a plurality of electrodes on a front surface of the semiconductor chip and the electrode members; and a resin sealing body which seals the semiconductor chip, the electrode members, and the coupling means, and in which a back surface of the semiconductor chip and the electrode members are exposed from a lower surface of the resin sealing body.
In addition, Japanese Patent Laid-Open No. 2005-294443 (Patent Document 2) discloses a semiconductor device in which an external terminal and a semiconductor chip which have been fabricated from a lead frame are electrically coupled to each other with a wire, and sealed with sealing resin, and in which an insulating resin layer is previously formed by coating or the like in contact with a back surface of the semiconductor chip, and in which the insulating resin layer is exposed at a lower surface side of the sealing resin, and exists over a same plane as a lower surface of the external terminal.
In addition, Japanese Patent Laid-Open No. 2009-76717 (Patent Document 3) discloses a technology in which a structure body having a lead electrode and a tab electrode is formed on an upper surface of a stainless steel plate by electroplating, the structure body including a nickel layer as a principal component, and in which subsequently, the above-described structure body is peeled off from the stainless steel plate.
Along with reduction in size and reduction in thickness of electronic equipments, reduction in size and reduction in thickness have been requested also in semiconductor devices (semiconductor packages) mounted in the electronic equipments.
In order to achieve reduction in size and reduction in thickness of a semiconductor device, for example, as shown in FIG. 3 in Japanese Patent Laid-Open No. 2002-76040, a structure is considered to be effective in which a die pad (a tab and chip mounting portion) for supporting a semiconductor chip is eliminated.
However, since the back surface of the semiconductor chip mounted in the semiconductor device is exposed from the sealing body in the above-described structure, a load (stress) is applied to the semiconductor chip, and a crack is easily generated in the semiconductor chip. If a thickness of the semiconductor chip is large, a serious problem does not occur even if slight loads are applied to the semiconductor chip, but the thickness of the semiconductor chip also tends to be smaller when there is a reduction in size and reduction in thickness of the semiconductor device. Therefore, in the semiconductor device in which reduction in size and reduction in thickness have progressed, there is a possibility that reliability of the semiconductor device is decreased due to the slight loads being applied to the semiconductor chip. In addition, when the back surface of the semiconductor chip is exposed from the sealing body, there is also a possibility that moisture enters from an interface of the sealing body and the semiconductor chip, and that reliability of the semiconductor device is decreased due to the moisture.
Consequently, the inventor of the present application has examined a manufacturing method for arranging a semiconductor chip over a mother substrate via an insulating resin layer (an adhesive film, an adhesive, an adhesive layer, or a sealing material) as shown in FIG. 2 in the above-described Japanese Patent Laid-Open No. 2005-294443. According to such manufacturing method, a back surface of the semiconductor chip can be protected since the insulating resin layer is placed on the back surface of the semiconductor chip. In addition, in accordance with such manufacturing method, since the die pad can be eliminated, it becomes possible to balance elimination of a die pad and protection of the back surface of the semiconductor chip. Accordingly, the above-described manufacturing method has been considered to be effective since not only reduction in size and reduction in thickness of the semiconductor device can be achieved, but also decrease in reliability of the semiconductor device can be suppressed.
However, the inventor of the present application has considered that it is necessary to make smaller a thickness of a lead used as an external terminal in order to achieve further reduction in size of the semiconductor device, and has examined the external terminal formed by using an electrolysis plating method as in the above-described Japanese Patent Laid-Open No. 2009-76717. Therefore, it has been found that the external terminal can be formed with a thickness approximately not more than half of the thickness of the lead including a part of a lead frame formed by patterning a conductive substrate as in the above-described Japanese Patent Laid-Open No. 2005-294443 by using the electrolysis plating method.
Incidentally, when an external terminal is formed by using the electrolysis plating method, a base material including a metal is used as a mother substrate. Therefore, after a sealing body which covers a semiconductor chip etc. is formed, the mother substrate has to be peeled off from the sealing body. However, as a result of examination by the inventor of the present application, a new problem has occurred that when a part of an insulating resin layer protrudes from a side surface of the semiconductor chip in a planar view, the part of the insulating resin layer protruding from the side surface of the semiconductor chip remains on the mother substrate at the time of peeling off the mother substrate from the sealing body, and cracks are generated on a part of a lower surface of the sealing body. This is because adhesion of the mother substrate including the metal to the insulating resin layer is larger than adhesion of the sealing body to the insulating resin layer. If there are cracks in the sealing body as described above, there has been concern that moisture enters into an interface of the sealing body and the semiconductor chip from the cracked portion, and reliability of the semiconductor device is decreased due to the moisture.